
return {

roms = {
	{ pos = {0, 0, 0}, size = {64, 16, 64}, signals = {
		"alulU", "alulT", "alulC", "alulB", "alulA", "alurIL", "alurIH", "alurVL",
		"alurVH", "alurSL", "alurSH", "alurQL", "alurQH", "alurPL", "alurPH", "alurU",
		"alurT", "alurC", "alurB", "alurA", "alur1", "alur2", "alurm1", "alurm2",
		"adrrhU", "adrrhC", "adrrlT", "adrrTX", "adrrlB", "adrrBX", "adwrhU", "adwrhC",
		"adwrlT", "adwrTX", "adwrlB", "adwrBX", "adwlI", "adwlV", "adwlS", "adwlQ",
		"adwlP", "adrlI", "adrlV", "adrlS", "adrlQ", "adrlP", "aluAdd", "adwSaveV",
		"aluRun", "aluRInv", "aluCinOn", "aluCinC", "memWriteAlur", "adrInc", "adwInc", "aluXor",
		"aluIor", "aluAnd", "memWriteAlur", "adrOut", "adrSaveI", "adwSaveP", "adwSaveQ", "adwSaveS",
	} },
	{ pos = {-34, 16, 0}, size = {32, 32, 8}, signals = {
		"aluSaveU", "aluSaveT", "aluSaveC", "aluSaveB", "aluSaveA", "aluSaveCarry", "aluSaveNZ", "always1",
	} },
	{ pos = {-34, 16, 17}, size = {32, 32, 32}, signals = {
		"_", "_", "_", "_", "_", "_", "_", "_",
		"_", "memSaveF", "memSaveNZ", "instrPre", "instrLoadPre", "always1", "instrLoadSel", "adrOut",
		"memWriteAlur", "memSave", "instrNext0NZ", "instrNext0Z", "instrNext0NC", "instrNext0C", "instrLoadSub", "instrLoad",
		"instrNext2", "instrNext1", "instrNext0", "memSaveU", "memSaveT", "memSaveC", "memSaveB", "memSaveA",
	} },
	{ pos = {66, 16, 0}, size = {32, 32, 32}, signals = {
		"adrr1", "adrrm1", "adrrm2", "adrr2", "adwrm1", "adwrm2", "adwr2", "adwr1",
		"memRead", "memWrite", "runFlgVal", "runFlgClk", "intFlgVal", "intFlgClk", "irqFlgClk", "always1",
		"aluShiftArith", "aluShiftRoll", "aluShiftRight", "aluShift", "alurF", "_", "_", "_",
		"_", "_", "_", "_", "_", "_", "_", "_",
	} },
},

operations = {
	base = {"always1"},
	
	instrNext = {"base","adrlI","adrInc","adrSaveI","loadInstr"},
	instrSub1 = {"base","instrLoadSub",                          "instrNext0"},
	instrSub2 = {"base","instrLoadSub",             "instrNext1",            },
	instrSub3 = {"base","instrLoadSub",             "instrNext1","instrNext0"},
	instrSub4 = {"base","instrLoadSub","instrNext2",                         },
	instrSub5 = {"base","instrLoadSub","instrNext2",             "instrNext0"},
	instrSub6 = {"base","instrLoadSub","instrNext2","instrNext1",            },
	instrSub7 = {"base","instrLoadSub","instrNext2","instrNext1","instrNext0"},
	instrSub23Cond = {"base","instrLoadSub","instrNext1"},
	instrSwapIV = {"base","adwlI","adwSaveV","adrlV","adrSaveI","loadInstr"},
	instrPreload = {"adrlI","adrInc","adrSaveI","adrOut","memRead","instrLoadSel","instrLoadPre"},
	instrNextPre = {"base","instrPre","instrLoad","instrLoadSub"},
	
	loadInstr = {"adrOut","memRead","instrLoadSel","instrLoad","instrLoadSub"},
	loadReg = {"adrOut","memRead","memSave"},
	storeReg = {"adrOut","memWrite","memWriteAlur"},
	loadRegT = {"loadReg","memSaveT"},
	
	pushReg = {"storeReg","adrlS","adwlS","adwInc","adwSaveS"},
	popReg = {"loadReg","adrlS","adrrm1","adwlS","adwrm1","adwSaveS"},
	pop161 = {"popReg","memSaveT"},
	pop162 = {"popReg","memSaveU"},
	
	loadImmed = {"adrlI","adrInc","adrSaveI","loadReg"},
	loadImmedT = {"loadImmed","memSaveT"},
	loadImm161 = {"loadImmed","memSaveU"},
	loadImm162 = {"loadImmed","memSaveT"},
	loadStackRel = {"adrlS","adrrTX","loadReg"},
	loadStackRelT = {"loadStackRel","memSaveT"},
	loadStackRelU = {"loadStackRel","memSaveU"},
	loadStackRel161 = {"loadStackRel",         "memSaveU"},
	loadStackRel162 = {"loadStackRel","adrInc","memSaveT"},
	storeStackRel = {"adrlS","adrrTX","storeReg"},
	storeStackRel161 = {"storeStackRel"         },
	storeStackRel162 = {"storeStackRel","adrInc"},
	storeStackRelU = {"storeStackRel","alurU"},
	load161 = {         "loadReg","memSaveU"},
	load162 = {"adrInc","loadReg","memSaveT"},
	store161 = {         "storeReg"},
	store162 = {"adrInc","storeReg"},
	loadUTU = {"adrrUT","loadReg","memSaveU"},
	storeUT = {"adrrUT","storeReg"},
	memSaveFlags = {"memSaveNZ"},
	
	adwrUT = {"adwrhU","adwrlT"},
	adrrUT = {"adrrhU","adrrlT"},
	adwrCB = {"adwrhC","adwrlB"},
	adwIncUT = {"adwrUT","adwInc"},
	adwP = {"adwlP","adwSaveP"},
	adwQ = {"adwlQ","adwSaveQ"},
	adwS = {"adwlS","adwSaveS"},
	incP  = {"adwP","adwInc"},
	incQ  = {"adwQ","adwInc"},
	incP2 = {"adwP","adwr2"},
	incQ2 = {"adwP","adwr2"},
	
	jmpRelT = {"instrNext","adrrTX"},
	jmpAbs = {"base","loadInstr","adrSaveI"},
	jmpAbsUT = {"jmpAbs","adrrUT"},
	jmpAbsP = {"jmpAbs","adrlP"},
	jmpAbsQ = {"jmpAbs","adrlQ"},
	saveRetAddr = {"adwlI","adwInc","adwSaveQ"},
	pushRetAddr1 = {"alurIH","pushReg"},
	pushRetAddr2 = {"alurIL","pushReg"},
	
	aluA = {"alulA","aluSaveA"},
	aluB = {"alulB","aluSaveB"},
	aluC = {"alulC","aluSaveC"},
	aluT = {"alulT","aluSaveT"},
	aluU = {"alulU","aluSaveU"},
	aluOpAdd = {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ"                     },
	aluOpAddC= {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ",          "aluCinC" },
	aluOpSub = {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ","aluRInv","aluCinOn"},
	aluOpSubC= {"aluRun","aluAdd","aluSaveCarry","aluSaveNZ","aluRInv","aluCinC" },
	aluOpAnd = {"aluRun","aluAnd"          , "aluSaveNZ"},
	aluOpIor = {"aluRun","aluIor"          , "aluSaveNZ"},
	aluOpXor = {"aluRun","aluXor"          , "aluSaveNZ"},
	aluOpAnn = {"aluRun","aluAnd","aluRInv", "aluSaveNZ"},
	aluOpCmp = {"aluOpSub"},
	aluOpInc = {"aluOpAdd","aluCinOn"},
	aluOpDec = {"aluOpAdd","aluRInv"},
	aluOpMov = {"aluAdd","aluSaveNZ"},
	aluOpShl = {"aluRun", "aluShift"                                               ,"aluSaveNZ"},
	aluOpShr = {"aluRun", "aluShift","aluShiftRight"                               ,"aluSaveNZ"},
	aluOpRol = {"aluRun", "aluShift",                "aluShiftRoll"                ,"aluSaveNZ"},
	aluOpRor = {"aluRun", "aluShift","aluShiftRight","aluShiftRoll"                ,"aluSaveNZ"},
	aluOpSra = {"aluRun", "aluShift","aluShiftRight",               "aluShiftArith","aluSaveNZ"},
	
	clearRegs = {
		"aluSaveA","aluSaveB","aluSaveC","aluSaveU","aluSaveT",
		"adwSaveP","adwSaveQ","adwSaveS","adwSaveV",
		"adrSaveI",
		"aluSaveNZ","aluSaveCarry",
	}
},

instructions = {
	{ category = "Control", catlet="C" },
	{ mnem="rst"        , opcode=0x00, {"base","intFlgClk","irqFlgClk","runFlgClk","runFlgVal","clearRegs","loadInstr"}, desc="Clear all registers and set I=0", ccode={"cpu.a=0; cpu.b=0; cpu.c=0; cpu.u=0; cpu.t=0; cpu.p=0; cpu.q=0; cpu.s=0; cpu.v=0; cpu.i=0; cpu.cf=0; cpu.nz=0; cpu.irq=0; cpu.ifg=0; cpu.rfg=1; cpu.ien=0; lni;"} },
	{ mnem="hlt"        , opcode=0xF0, {"runFlgClk","instrNext"}, desc="Halt non-interrupt execution", ccode={"cpu.rfg=0; lni;"} },
	{ mnem="run"        , opcode=0xF1, {"runFlgClk","runFlgVal","instrNext"}, desc ="Resume non-interrupt execution", ccode={"cpu.rfg=1; lni;"} },
	{ mnem="int"        , opcode=0xF2, {"instrSwapIV","intFlgVal","intFlgClk","irqFlgClk"}, ccode={"cpu.irq=0; cpu.ifg=1; int t=cpu.i; cpu.i=cpu.v; cpu.v=(t-1)%65536; lni;"} },
	{ mnem="brk"        , opcode=0xF3, {"instrSwapIV","adwInc","intFlgVal","intFlgClk"}, desc="Trigger interrupt", ccode={"cpu.ifg=1; int t=cpu.i; cpu.i=cpu.v; cpu.v=t; lni;"} },
	{ mnem="irt"        , opcode=0xF4, {"instrSwapIV","adwInc","intFlgClk"}, desc="Return from interrupt", ccode={"cpu.ifg=0; int t=cpu.i; cpu.i=cpu.v; cpu.v=t; lni;"} },
	{ mnem="nop"        , opcode=0xFF, {"instrNext"}, desc="Do nothing", ccode={"lni;"}, },
	{ mnem="ien"        , opcode=0xF5, {"instrNext"}, desc="Enbale interrupts", ccode={"cpu.ien=1; lni;"}, }, -- todo
	{ mnem="idi"        , opcode=0xF6, {"instrNext"}, desc="Disable interrupts", ccode={"cpu.ien=0; lni;"}, }, -- todo
	
	{ category = "16-bit Inc/Dec", catlet="I" },
	{ mnem="inc p"      , opcode=0x12, {"adwlP","adwInc","adwSaveP","instrNext"}, desc="P++", ccode={"cpu.p++; lni;"} },
	{ mnem="dec p"      , opcode=0x15, {"adwlP","adwrm1","adwSaveP","instrNext"}, desc="P--", ccode={"cpu.p--; lni;"} },
	{ mnem="inc q"      , opcode=0x13, {"adwlQ","adwInc","adwSaveQ","instrNext"}, desc="Q++", ccode={"cpu.q++; lni;"} },
	{ mnem="dec q"      , opcode=0x16, {"adwlQ","adwrm1","adwSaveQ","instrNext"}, desc="Q--", ccode={"cpu.q--; lni;"} },
	
	{ category = "8-bit Unary", catlet="U" },
	{ mnem="inc a"      , opcode=0x10,                                                            {"aluA","alur1" ,"aluOpAdd" ,"instrNext"}, desc="A++, set flags"  , ccode={"addf(cpu.a, 1    ); lni;"} },
	{ mnem="dec a"      , opcode=0x11,                                                            {"aluA","alurm1","aluOpAdd" ,"instrNext"}, desc="A--, set flags"  , ccode={"addf(cpu.a,-1    ); lni;"} },
	{ mnem="icc a"      , opcode=0x1B,                                                            {"aluA",         "aluOpAddC","instrNext"}, desc="A+=CF, set flags", ccode={"addf(cpu.a,cpu.cf); lni;"} },
	{ mnem="inc b"      , opcode=0x19,                                                            {"aluB","alur1" ,"aluOpAdd" ,"instrNext"}, desc="B++, set flags"  , ccode={"addf(cpu.b, 1    ); lni;"} },
	{ mnem="dec b"      , opcode=0x1A,                                                            {"aluB","alurm1","aluOpAdd" ,"instrNext"}, desc="B--, set flags"  , ccode={"addf(cpu.b,-1    ); lni;"} },
	{ mnem="icc b"      , opcode=0x1C,                                                            {"aluB",         "aluOpAddC","instrNext"}, desc="B+=CF, set flags", ccode={"addf(cpu.b,cpu.cf); lni;"} },
	{ mnem="inc c"      , opcode=0x17,                                                            {"aluC","alur1" ,"aluOpAdd" ,"instrNext"}, desc="C++, set flags"  , ccode={"addf(cpu.c, 1    ); lni;"} },
	{ mnem="dec c"      , opcode=0x18,                                                            {"aluC","alurm1","aluOpAdd" ,"instrNext"}, desc="C--, set flags"  , ccode={"addf(cpu.c,-1    ); lni;"} },
	{ mnem="icc c"      , opcode=0x1D,                                                            {"aluC",         "aluOpAddC","instrNext"}, desc="C+=CF, set flags", ccode={"addf(cpu.c,cpu.cf); lni;"} },
	{ mnem="tst a"      , opcode=0x14,                                                            {"alulA",        "aluOpCmp" ,"instrNext"}, desc="Set flags according to A-0", ccode={"tst(cpu.a); lni;"} },
	{ mnem="tst b"      , opcode=0x1E,                                                            {"alulB",        "aluOpCmp" ,"instrNext"}, desc="Set flags according to B-0", ccode={"tst(cpu.b); lni;"} },
	{ mnem="tst c"      , opcode=0x1F,                                                            {"alulC",        "aluOpCmp" ,"instrNext"}, desc="Set flags according to C-0", ccode={"tst(cpu.c); lni;"} },
	{ mnem="inc *s+imm8", opcode=0x2B, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alur1" ,"aluOpAdd" ,"instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)++, set flags"  , ccode={"loadimmedt","loadstackrelu","instrpreload; addf(cpu.u, 1    );","instrloadpre"} },
	{ mnem="dec *s+imm8", opcode=0x2C, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alurm1","aluOpAdd" ,"instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)--, set flags"  , ccode={"loadimmedt","loadstackrelu","instrpreload; addf(cpu.u,-1    );","instrloadpre"} },
	{ mnem="icc *s+imm8", opcode=0x2D, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU",         "aluOpAddC","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="*(S+imm8)+=CF, set flags", ccode={"loadimmedt","loadstackrelu","instrpreload; addf(cpu.u,cpu.cf);","instrloadpre"} },
	{ mnem="tst *s+imm8", opcode=0x2E, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"alulU",        "aluOpCmp" ,"instrNext"},                                                   desc="Set flags according to *(S+imm8)-0", ccode={"loadimmedt","loadstackrelu","tst(cpu.u); lni;"} },
	
	{ category = "16-bit Arithmetic", catlet = "X"},
	{ mnem="adp imm8"   , opcode=0x4A, {"loadImmedT","instrSub1"}, {"adwP","adwrTX","instrNext"}, desc="P+=imm8 signed", ccode={"loadimmedt","cpu.p+=signed8(cpu.t); lni;"} },
	{ mnem="adq imm8"   , opcode=0x4B, {"loadImmedT","instrSub1"}, {"adwQ","adwrTX","instrNext"}, desc="Q+=imm8 signed", ccode={"loadimmedt","cpu.q+=signed8(cpu.t); lni;"} },
	{ mnem="ads imm8"   , opcode=0x4C, {"loadImmedT","instrSub1"}, {"adwS","adwrTX","instrNext"}, desc="S+=imm8 signed", ccode={"loadimmedt","cpu.s+=signed8(cpu.t); lni;"} },
	{ mnem="adp b"      , opcode=0xE6, {"adwP","adwrBX","instrNext"}, desc="P+=B signed", ccode={"cpu.p+=signed8(cpu.b); lni;"} },
	{ mnem="adq b"      , opcode=0xE7, {"adwQ","adwrBX","instrNext"}, desc="Q+=B signed", ccode={"cpu.q+=signed8(cpu.b); lni;"} },
	{ mnem="ads b"      , opcode=0xE8, {"adwS","adwrBX","instrNext"}, desc="S+=B signed", ccode={"cpu.s+=signed8(cpu.b); lni;"} },
	
	{ category = "8-bit Arithmetic/Logic", catlet="A" },
	{ mnem="add imm8"   , opcode=0x24, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAdd" ,"instrNext"}, desc="A+=imm8, set flags"                , ccode={"loadimmedt","addf(cpu.a,cpu.t); lni;"} },
	{ mnem="adb imm8"   , opcode=0x72, {"loadImmedT","instrSub1"},                                {"aluB", "alurT","aluOpAdd" ,"instrNext"}, desc="B+=imm8, set flags"                , ccode={"loadimmedt","addf(cpu.b,cpu.t); lni;"} },
	{ mnem="adc imm8"   , opcode=0x73, {"loadImmedT","instrSub1"},                                {"aluC", "alurT","aluOpAdd" ,"instrNext"}, desc="C+=imm8, set flags"                , ccode={"loadimmedt","addf(cpu.c,cpu.t); lni;"} },
	{ mnem="sub imm8"   , opcode=0x70, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpSub" ,"instrNext"}, desc="A-=imm8, set flags"                , ccode={"loadimmedt","subf(cpu.a,cpu.t); lni;"} },
	{ mnem="sbb imm8"   , opcode=0x99, {"loadImmedT","instrSub1"},                                {"aluB", "alurT","aluOpSub" ,"instrNext"}, desc="B-=imm8, set flags"                , ccode={"loadimmedt","subf(cpu.b,cpu.t); lni;"} },
	{ mnem="sbc imm8"   , opcode=0x9A, {"loadImmedT","instrSub1"},                                {"aluC", "alurT","aluOpSub" ,"instrNext"}, desc="C-=imm8, set flags"                , ccode={"loadimmedt","subf(cpu.c,cpu.t); lni;"} },
	{ mnem="acc imm8"   , opcode=0x78, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAddC","instrNext"}, desc="A+=imm8+CF, set flags"             , ccode={"loadimmedt","addf(cpu.a,cpu.t+cpu.cf); lni;"} },
	{ mnem="scc imm8"   , opcode=0x79, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpSubC","instrNext"}, desc="A-=imm8+CF, set flags"             , ccode={"loadimmedt","addf(cpu.a,-cpu.t+cpu.cf); lni;"} },
	{ mnem="cmp imm8"   , opcode=0x71, {"loadImmedT","instrSub1"},                                {"alulA","alurT","aluOpSub" ,"instrNext"}, desc="set flags according to A-imm8"     , ccode={"loadimmedt","cmpf(cpu.a,cpu.t); lni;"} },
	{ mnem="and imm8"   , opcode=0x74, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAnd" ,"instrNext"}, desc="A&=imm8, set zero flag"            , ccode={"loadimmedt","cpu.a&=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="ior imm8"   , opcode=0x75, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpIor" ,"instrNext"}, desc="A|=imm8, set zero flag"            , ccode={"loadimmedt","cpu.a|=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="xor imm8"   , opcode=0x76, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpXor" ,"instrNext"}, desc="A^=imm8, set zero flag"            , ccode={"loadimmedt","cpu.a^=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="ann imm8"   , opcode=0x77, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAnn" ,"instrNext"}, desc="A&=~imm8, set zero flag"           , ccode={"loadimmedt","cpu.a&=~cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="shl imm8"   , opcode=0xD0, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpShl" ,"instrNext"}, desc="A<<=imm8, set zero flag"           , ccode={"loadimmedt","cpu.a<<=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="shr imm8"   , opcode=0xD1, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpShr" ,"instrNext"}, desc="A>>=imm8, set zero flag"           , ccode={"loadimmedt","cpu.a>>=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="rol imm8"   , opcode=0xD2, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpRol" ,"instrNext"}, desc="A<<<=imm8, set zero flag"          , ccode={"loadimmedt","cpu.a=rol(cpu.a,cpu.t); setzf(cpu.a); lni;"} },
	{ mnem="ror imm8"   , opcode=0xD3, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpRor" ,"instrNext"}, desc="A>>>=imm8, set zero flag"          , ccode={"loadimmedt","cpu.a=ror(cpu.a,cpu.t); setzf(cpu.a); lni;"} },
	{ mnem="sra imm8"   , opcode=0xD4, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpSra" ,"instrNext"}, desc="A>>a=imm8, set zero flag"          , ccode={"loadimmedt","cpu.a=sra(cpu.a,cpu.t); setzf(cpu.a); lni;"} },
	{ mnem="add *s+imm8", opcode=0xAE, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAdd" ,"instrNext"}, desc="A+=*(S+imm8), set flags"           , ccode={"loadimmedt","loadstackrelu","addf(cpu.a,cpu.u); lni;"} },
	{ mnem="adb *s+imm8", opcode=0x9B, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluOpAdd" ,"instrNext"}, desc="B+=*(S+imm8), set flags"           , ccode={"loadimmedt","loadstackrelu","addf(cpu.b,cpu.u); lni;"} },
	{ mnem="adc *s+imm8", opcode=0x9C, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluOpAdd" ,"instrNext"}, desc="C+=*(S+imm8), set flags"           , ccode={"loadimmedt","loadstackrelu","addf(cpu.c,cpu.u); lni;"} },
	{ mnem="sub *s+imm8", opcode=0xAF, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSub" ,"instrNext"}, desc="A-=*(S+imm8), set flags"           , ccode={"loadimmedt","loadstackrelu","subf(cpu.a,cpu.u); lni;"} },
	{ mnem="sbb *s+imm8", opcode=0x9D, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluOpSub" ,"instrNext"}, desc="B-=*(S+imm8), set flags"           , ccode={"loadimmedt","loadstackrelu","subf(cpu.b,cpu.u); lni;"} },
	{ mnem="sbc *s+imm8", opcode=0x9E, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluOpSub" ,"instrNext"}, desc="C-=*(S+imm8), set flags"           , ccode={"loadimmedt","loadstackrelu","subf(cpu.c,cpu.u); lni;"} },
	{ mnem="acc *s+imm8", opcode=0xB5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAddC","instrNext"}, desc="A+=*(S+imm8)+CF, set flags"        , ccode={"loadimmedt","loadstackrelu","addf(cpu.a,cpu.u+cpu.cf); lni;"} },
	{ mnem="scc *s+imm8", opcode=0xB7, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSubC","instrNext"}, desc="A-=*(S+imm8)+CF, set flags"        , ccode={"loadimmedt","loadstackrelu","addf(cpu.a,-cpu.u+cpu.cf); lni;"} },
	{ mnem="cmp *s+imm8", opcode=0xB0, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"alulA","alurT","aluOpSub" ,"instrNext"}, desc="set flags according to A-*(S+imm8)", ccode={"loadimmedt","loadstackrelu","cmpf(cpu.a,cpu.u); lni;"} },
	{ mnem="and *s+imm8", opcode=0xB1, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAnd" ,"instrNext"}, desc="A&=*(S+imm8), set zero flag"       , ccode={"loadimmedt","loadstackrelu","cpu.a&=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="ior *s+imm8", opcode=0xB2, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpIor" ,"instrNext"}, desc="A|=*(S+imm8), set zero flag"       , ccode={"loadimmedt","loadstackrelu","cpu.a|=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="xor *s+imm8", opcode=0xB3, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpXor" ,"instrNext"}, desc="A^=*(S+imm8), set zero flag"       , ccode={"loadimmedt","loadstackrelu","cpu.a^=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="ann *s+imm8", opcode=0xB4, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAnn" ,"instrNext"}, desc="A&=~*(S+imm8), set zero flag"      , ccode={"loadimmedt","loadstackrelu","cpu.a&=~cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="shl *s+imm8", opcode=0xD5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpShl" ,"instrNext"}, desc="A<<=*(S+imm8), set zero flag"      , ccode={"loadimmedt","loadstackrelu","cpu.a<<=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="shr *s+imm8", opcode=0xD6, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpShr" ,"instrNext"}, desc="A<<=*(S+imm8), set zero flag"      , ccode={"loadimmedt","loadstackrelu","cpu.a>>=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="rol *s+imm8", opcode=0xD7, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpRol" ,"instrNext"}, desc="A<<<=*(S+imm8), set zero flag"     , ccode={"loadimmedt","loadstackrelu","cpu.a=rol(cpu.a,cpu.u); setzf(cpu.a); lni;"} },
	{ mnem="ror *s+imm8", opcode=0xD8, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpRor" ,"instrNext"}, desc="A>>>=*(S+imm8), set zero flag"     , ccode={"loadimmedt","loadstackrelu","cpu.a=ror(cpu.a,cpu.u); setzf(cpu.a); lni;"} },
	{ mnem="sra *s+imm8", opcode=0xD9, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSra" ,"instrNext"}, desc="A>>a=*(S+imm8), set zero flag"     , ccode={"loadimmedt","loadstackrelu","cpu.a=sra(cpu.a,cpu.u); setzf(cpu.a); lni;"} },
	{ mnem="add b"      , opcode=0xA0,                                                            {"aluA", "alurB","aluOpAdd" ,"instrNext"}, desc="A+=B, set flags"                   , ccode={"addf(cpu.a,cpu.b); lni;"} },
	{ mnem="adc b"      , opcode=0x9F,                                                            {"aluC", "alurB","aluOpAdd" ,"instrNext"}, desc="C+=B, set flags"                   , ccode={"addf(cpu.c,cpu.b); lni;"} },
	{ mnem="sub b"      , opcode=0xA1,                                                            {"aluA", "alurB","aluOpSub" ,"instrNext"}, desc="A-=B, set flags"                   , ccode={"subf(cpu.a,cpu.b); lni;"} },
	{ mnem="sbc b"      , opcode=0xB6,                                                            {"aluC", "alurB","aluOpSub" ,"instrNext"}, desc="C-=B, set flags"                   , ccode={"subf(cpu.c,cpu.b); lni;"} },
	{ mnem="acc b"      , opcode=0xB8,                                                            {"aluA", "alurB","aluOpAddC","instrNext"}, desc="A+=B+CF, set flags"                , ccode={"addf(cpu.a,cpu.b+cpu.cf); lni;"} },
	{ mnem="scc b"      , opcode=0xB9,                                                            {"aluA", "alurB","aluOpSubC","instrNext"}, desc="A-=B+CF, set flags"                , ccode={"addf(cpu.a,-cpu.b+cpu.cf); lni;"} },
	{ mnem="cmp b"      , opcode=0xA2,                                                            {"alulA","alurB","aluOpSub" ,"instrNext"}, desc="set flags according to A-B"        , ccode={"cmpf(cpu.a,cpu.b); lni;"} },
	{ mnem="and b"      , opcode=0xA3,                                                            {"aluA", "alurB","aluOpAnd" ,"instrNext"}, desc="A&=B, set zero flag"               , ccode={"cpu.a&=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="ior b"      , opcode=0xA4,                                                            {"aluA", "alurB","aluOpIor" ,"instrNext"}, desc="A|=B, set zero flag"               , ccode={"cpu.a|=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="xor b"      , opcode=0xA5,                                                            {"aluA", "alurB","aluOpXor" ,"instrNext"}, desc="A^=B, set zero flag"               , ccode={"cpu.a^=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="ann b"      , opcode=0xA6,                                                            {"aluA", "alurB","aluOpAnn" ,"instrNext"}, desc="A&=~B, set zero flag"              , ccode={"cpu.a&=~cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="shl b"      , opcode=0xDA,                                                            {"aluA", "alurB","aluOpShl" ,"instrNext"}, desc="A<<=B, set zero flag"              , ccode={"cpu.a<<=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="shr b"      , opcode=0xDB,                                                            {"aluA", "alurB","aluOpShr" ,"instrNext"}, desc="A>>=B, set zero flag"              , ccode={"cpu.a>>=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="rol b"      , opcode=0xDC,                                                            {"aluA", "alurB","aluOpRol" ,"instrNext"}, desc="A<<<=B, set zero flag"             , ccode={"cpu.a=rol(cpu.a,cpu.b); setzf(cpu.a); lni;"} },
	{ mnem="ror b"      , opcode=0xDD,                                                            {"aluA", "alurB","aluOpRor" ,"instrNext"}, desc="A>>>=B, set zero flag"             , ccode={"cpu.a=ror(cpu.a,cpu.b); setzf(cpu.a); lni;"} },
	{ mnem="sra b"      , opcode=0xDE,                                                            {"aluA", "alurB","aluOpSra" ,"instrNext"}, desc="A>>a=B, set zero flag"             , ccode={"cpu.a=sra(cpu.a,cpu.b); setzf(cpu.a); lni;"} },
	{ mnem="add c"      , opcode=0xA7,                                                            {"aluA", "alurC","aluOpAdd" ,"instrNext"}, desc="A+=C, set flags"                   , ccode={"addf(cpu.a,cpu.c); lni;"} },
	{ mnem="adb c"      , opcode=0xBD,                                                            {"aluB", "alurC","aluOpAdd" ,"instrNext"}, desc="B+=C, set flags"                   , ccode={"addf(cpu.b,cpu.c); lni;"} },
	{ mnem="sub c"      , opcode=0xA8,                                                            {"aluA", "alurC","aluOpSub" ,"instrNext"}, desc="A-=C, set flags"                   , ccode={"subf(cpu.a,cpu.c); lni;"} },
	{ mnem="sbb c"      , opcode=0xBC,                                                            {"aluB", "alurC","aluOpSub" ,"instrNext"}, desc="B-=C, set flags"                   , ccode={"subf(cpu.b,cpu.c); lni;"} },
	{ mnem="acc c"      , opcode=0xBA,                                                            {"aluA", "alurC","aluOpAddC","instrNext"}, desc="A+=C+CF, set flags"                , ccode={"addf(cpu.a,cpu.c+cpu.cf); lni;"} },
	{ mnem="scc c"      , opcode=0xBB,                                                            {"aluA", "alurC","aluOpSubC","instrNext"}, desc="A-=C+CF, set flags"                , ccode={"addf(cpu.a,-cpu.c+cpu.cf); lni;"} },
	{ mnem="cmp c"      , opcode=0xA9,                                                            {"alulA","alurC","aluOpSub" ,"instrNext"}, desc="set flags according to A-C"        , ccode={"cmpf(cpu.a,cpu.c); lni;"} },
	{ mnem="and c"      , opcode=0xAA,                                                            {"aluA", "alurC","aluOpAnd" ,"instrNext"}, desc="A&=C, set zero flag"               , ccode={"cpu.a&=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="ior c"      , opcode=0xAB,                                                            {"aluA", "alurC","aluOpIor" ,"instrNext"}, desc="A|=C, set zero flag"               , ccode={"cpu.a|=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="xor c"      , opcode=0xAC,                                                            {"aluA", "alurC","aluOpXor" ,"instrNext"}, desc="A^=C, set zero flag"               , ccode={"cpu.a^=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="ann c"      , opcode=0xAD,                                                            {"aluA", "alurC","aluOpAnn" ,"instrNext"}, desc="A&=~C, set zero flag"              , ccode={"cpu.a&=~cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="shl c"      , opcode=0xDF,                                                            {"aluA", "alurC","aluOpShl" ,"instrNext"}, desc="A<<=C, set zero flag"              , ccode={"cpu.a<<=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="shr c"      , opcode=0x4D,                                                            {"aluA", "alurC","aluOpShr" ,"instrNext"}, desc="A>>=C, set zero flag"              , ccode={"cpu.a>>=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="rol c"      , opcode=0x3E,                                                            {"aluA", "alurC","aluOpRol" ,"instrNext"}, desc="A<<<=C, set zero flag"             , ccode={"cpu.a=rol(cpu.a,cpu.c); setzf(cpu.a); lni;"} },
	{ mnem="ror c"      , opcode=0x3F,                                                            {"aluA", "alurC","aluOpRor" ,"instrNext"}, desc="A>>>=C, set zero flag"             , ccode={"cpu.a=ror(cpu.a,cpu.c); setzf(cpu.a); lni;"} },
	{ mnem="sra c"      , opcode=0x2F,                                                            {"aluA", "alurC","aluOpSra" ,"instrNext"}, desc="A>>a=C, set zero flag"             , ccode={"cpu.a=sra(cpu.a,cpu.c); setzf(cpu.a); lni;"} },
	{ mnem="adb a"      , opcode=0xBE,                                                            {"aluB", "alurA","aluOpAdd" ,"instrNext"}, desc="B+=A, set flags"                   , ccode={"addf(cpu.b,cpu.a); lni;"} },
	{ mnem="sbb a"      , opcode=0xBF,                                                            {"aluB", "alurA","aluOpSub" ,"instrNext"}, desc="B-=A, set flags"                   , ccode={"subf(cpu.b,cpu.a); lni;"} },
	{ mnem="adc a"      , opcode=0x4E,                                                            {"aluC", "alurA","aluOpAdd" ,"instrNext"}, desc="C+=A, set flags"                   , ccode={"addf(cpu.c,cpu.a); lni;"} },
	{ mnem="sbc a"      , opcode=0x4F,                                                            {"aluC", "alurA","aluOpSub" ,"instrNext"}, desc="C-=A, set flags"                   , ccode={"subf(cpu.c,cpu.a); lni;"} },
	
	{ category = "Jumps", catlet="J" },
	{ mnem="jmp imm16"  , opcode=0x60, jmp=true, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"jmpAbsUT"              }, desc="I=imm16"     , ccode={"loadimm161","loadimm162","jmpabsut"} },
	{ mnem="jsr imm16"  , opcode=0x63, jmp=true, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"jmpAbsUT","saveRetAddr"}, desc="I=imm16, Q=I", ccode={"loadimm161","loadimm162","jmpabsut saveretaddr"} },
	{ mnem="jss imm16"  , opcode=0xE2, jmp=true, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"pushRetAddr1","instrSub3"}, {"pushRetAddr2","instrSub4"}, {"jmpAbsUT"}, desc="I=imm16, *(S++++)=I-1", ccode={"loadimm161","loadimm162","pushretaddr1","pushretaddr2","jmpabsut"} },
	{ mnem="jmp p"      , opcode=0x64, {"jmpAbsP"              }, desc="I=P"     , ccode={"jmpabsp"} },
	{ mnem="jmp q"      , opcode=0x66, {"jmpAbsQ"              }, desc="I=Q"     , ccode={"jmpabsq"} },
	{ mnem="jsr p"      , opcode=0x65, {"jmpAbsP","saveRetAddr"}, desc="I=P, Q=I", ccode={"jmpabsp","saveretaddr"} },
	{ mnem="jsr q"      , opcode=0x67, {"jmpAbsQ","saveRetAddr"}, desc="I=Q, Q=I", ccode={"jmpabsq","saveretaddr"} },
	{ mnem="jss p"      , opcode=0xE4, {"pushRetAddr1","instrSub1"}, {"pushRetAddr2","instrSub2"}, {"jmpAbsP"}, desc="I=P, *(S++++)=I-1", ccode={"pushretaddr1","pushretaddr2","jmpabsp"} },
	{ mnem="jss q"      , opcode=0xE5, {"pushRetAddr1","instrSub1"}, {"pushRetAddr2","instrSub2"}, {"jmpAbsQ"}, desc="I=Q, *(S++++)=I-1", ccode={"pushretaddr1","pushretaddr2","jmpabsq"} },
	{ mnem="rts"        , opcode=0xE1, {"pop161","instrSub1"}, {"pop162","instrSub2"}, {"jmpAbsUT","adrInc"}, desc="I=*(----S)+1", ccode={"pop161","pop162","jmpabsutplus1"} },
	{ mnem="jpr imm8"   , opcode=0x31, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub1"}, {"jmpRelT"}, desc="I+=imm8", ccode={"loadimmedt","jmprelt"} },
	{ mnem="jnz imm8"   , opcode=0x30, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub23Cond","instrNext0NZ"               }, {}, {"instrNext"}, {"jmpRelT"}, desc="I+=imm8 if !Zero"       , ccode={"loadimmedt","if( cpu.nz               ) { jmprelt } else { lni }"} },
	{ mnem="jpz imm8"   , opcode=0x32, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub23Cond","instrNext0Z"                }, {}, {"instrNext"}, {"jmpRelT"}, desc="I+=imm8 if Zero"        , ccode={"loadimmedt","if(!cpu.nz               ) { jmprelt } else { lni }"} },
	{ mnem="jlt imm8"   , opcode=0x33, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub23Cond","instrNext0NC"               }, {}, {"instrNext"}, {"jmpRelT"}, desc="I+=imm8 if !Carry"      , ccode={"loadimmedt","if(!cpu.cf               ) { jmprelt } else { lni }"} },
	{ mnem="jge imm8"   , opcode=0x34, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub23Cond","instrNext0C"                }, {}, {"instrNext"}, {"jmpRelT"}, desc="I+=imm8 if Carry"       , ccode={"loadimmedt","if( cpu.cf               ) { jmprelt } else { lni }"} },
	{ mnem="jgt imm8"   , opcode=0x35, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub23Cond","instrNext0NC","instrNext0Z"}, {}, {"jmpRelT"}, {"instrNext"}, desc="I+=imm8 if !Zero & Carry", ccode={"loadimmedt","if(  cpu.nz &&    cpu.cf ) { jmprelt } else { lni }"} },
	{ mnem="jle imm8"   , opcode=0x36, jmp=true, rel=true, ncycles=2, {"loadImmed","memSaveT","instrSub23Cond","instrNext0NC","instrNext0Z"}, {}, {"instrNext"}, {"jmpRelT"}, desc="I+=imm8 if Zero | !Carry", ccode={"loadimmedt","if((!cpu.nz) || (!cpu.cf)) { jmprelt } else { lni }"} },
	
	{ category = "Stack", catlet="S" },
	{ mnem="psh a"      , opcode=0x40, {"pushReg","alurA","instrSub1"}, {"instrNext"}, desc="*(S++)=A", ccode={"pushbyte(cpu.a);","lni;"} },
	{ mnem="psh b"      , opcode=0x44, {"pushReg","alurB","instrSub1"}, {"instrNext"}, desc="*(S++)=B", ccode={"pushbyte(cpu.b);","lni;"} },
	{ mnem="psh c"      , opcode=0x45, {"pushReg","alurC","instrSub1"}, {"instrNext"}, desc="*(S++)=C", ccode={"pushbyte(cpu.c);","lni;"} },
	{ mnem="psh f"      , opcode=0xE9, {"pushReg","alurF","instrSub1"}, {"instrNext"}, desc="*(S++)=F", ccode={"int f = cpu.nz | (cpu.cf<<1); pushbyte(f);","lni;"} },
	{ mnem="psh p"      , opcode=0x41, {"pushReg","alurPH","instrSub1"}, {"pushReg","alurPL","instrSub2"}, {"instrNext"}, desc="*(S++++)=P", ccode={"push161(cpu.p);","push162(cpu.p);","lni;"} },
	{ mnem="psh q"      , opcode=0x46, {"pushReg","alurQH","instrSub1"}, {"pushReg","alurQL","instrSub2"}, {"instrNext"}, desc="*(S++++)=Q", ccode={"push161(cpu.q);","push162(cpu.q);","lni;"} },
	{ mnem="pop a"      , opcode=0x42, {"popReg","memSaveA","instrSub1"}, {"instrNext"}, desc="A=*(--S)", ccode={"cpu.a=popbyte;","lni;"} },
	{ mnem="pop b"      , opcode=0x47, {"popReg","memSaveB","instrSub1"}, {"instrNext"}, desc="B=*(--S)", ccode={"cpu.b=popbyte;","lni;"} },
	{ mnem="pop c"      , opcode=0x48, {"popReg","memSaveC","instrSub1"}, {"instrNext"}, desc="C=*(--S)", ccode={"cpu.c=popbyte;","lni;"} },
	{ mnem="pop f"      , opcode=0xEA, {"popReg","memSaveF","instrSub1"}, {"instrNext"}, desc="F=*(--S)", ccode={"int f=popbyte; cpu.nz = f&1; cpu.cf = (f>>1)&1;","lni;"} },
	{ mnem="pop p"      , opcode=0x43, {"pop161","instrSub1"}, {"pop162","instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*(----S)", ccode={"pop161","pop162","cpu.p=wordut; lni;"} },
	{ mnem="pop q"      , opcode=0x49, {"pop161","instrSub1"}, {"pop162","instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*(----S)", ccode={"pop161","pop162","cpu.q=wordut; lni;"} },
	{ mnem="psh imm8"   , opcode=0x3B, {"loadImmedT","instrSub1"}, {"pushReg","alurT","instrSub2"}, {"instrNext"}, desc="*(S++)=imm8", ccode={"loadimmedt;","pushbyte(cpu.t);","lni;"} },
	{ mnem="phw imm16"  , opcode=0x3C, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"pushReg","alurU","instrSub3"}, {"pushReg","alurT","instrSub4"}, {"instrNext"}, desc="*(S++++)=imm16", ccode={"loadimm161","loadimm162","pushbyte(cpu.u);","pushbyte(cpu.t);","lni;"} }, -- 0x3D
	
	{ category = "8-bit Load/Store", catlet="B" },
	{ mnem="lda imm8"   , opcode=0x20,                             {"loadImmed",   "memSaveA","memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=imm8, update zero flag", ccode={"cpu.a=loadimmed; setzf(cpu.a);","lni;"} },
	{ mnem="ldb imm8"   , opcode=0x26,                             {"loadImmed",   "memSaveB","memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=imm8, update zero flag", ccode={"cpu.b=loadimmed; setzf(cpu.b);","lni;"} },
	{ mnem="ldc imm8"   , opcode=0x27,                             {"loadImmed",   "memSaveC","memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=imm8, update zero flag", ccode={"cpu.c=loadimmed; setzf(cpu.c);","lni;"} },
	{ mnem="lda *s+imm8", opcode=0x28, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveA","memSaveFlags","instrSub2"}, {"instrNext"}, desc="A=*s+imm8, update zero flag", ccode={"loadimmedt;","cpu.a=loadstackrel; setzf(cpu.a);","lni;"} },
	{ mnem="ldb *s+imm8", opcode=0x29, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveB","memSaveFlags","instrSub2"}, {"instrNext"}, desc="B=*s+imm8, update zero flag", ccode={"loadimmedt;","cpu.b=loadstackrel; setzf(cpu.b);","lni;"} },
	{ mnem="ldc *s+imm8", opcode=0x2A, {"loadImmedT","instrSub1"}, {"loadStackRel","memSaveC","memSaveFlags","instrSub2"}, {"instrNext"}, desc="C=*s+imm8, update zero flag", ccode={"loadimmedt;","cpu.c=loadstackrel; setzf(cpu.c);","lni;"} },
	{ mnem="sta *s+imm8", opcode=0x96, {"loadImmedT","instrSub1"}, {"storeStackRel","alurA","instrSub2"}, {"instrNext"}, desc="*s+imm8=A", ccode={"loadimmedt;","storestackrel(cpu.a);","lni;"} },
	{ mnem="stb *s+imm8", opcode=0x97, {"loadImmedT","instrSub1"}, {"storeStackRel","alurB","instrSub2"}, {"instrNext"}, desc="*s+imm8=B", ccode={"loadimmedt;","storestackrel(cpu.a);","lni;"} },
	{ mnem="stc *s+imm8", opcode=0x98, {"loadImmedT","instrSub1"}, {"storeStackRel","alurC","instrSub2"}, {"instrNext"}, desc="*s+imm8=C", ccode={"loadimmedt;","storestackrel(cpu.a);","lni;"} },
	{ mnem="lda *imm16" , opcode=0x51, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveA","memSaveFlags","instrSub3"}, {"instrNext"}, desc="A=*imm16, update zero flag", ccode={"loadimm161","loadimm162","cpu.a=loadut; setzf(cpu.a);","lni;"} },
	{ mnem="ldb *imm16" , opcode=0x56, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveB","memSaveFlags","instrSub3"}, {"instrNext"}, desc="B=*imm16, update zero flag", ccode={"loadimm161","loadimm162","cpu.b=loadut; setzf(cpu.b);","lni;"} },
	{ mnem="ldc *imm16" , opcode=0x57, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","loadReg","memSaveC","memSaveFlags","instrSub3"}, {"instrNext"}, desc="C=*imm16, update zero flag", ccode={"loadimm161","loadimm162","cpu.c=loadut; setzf(cpu.c);","lni;"} },
	{ mnem="sta *imm16" , opcode=0x50, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurA","instrSub3"}, {"instrNext"}, desc="*imm16=A", ccode={"loadimm161","loadimm162","storeut(cpu.a);","lni;"} },
	{ mnem="stb *imm16" , opcode=0x58, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurB","instrSub3"}, {"instrNext"}, desc="*imm16=B", ccode={"loadimm161","loadimm162","storeut(cpu.b);","lni;"} },
	{ mnem="stc *imm16" , opcode=0x59, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2",}, {"adrrUT","storeReg","alurC","instrSub3"}, {"instrNext"}, desc="*imm16=C", ccode={"loadimm161","loadimm162","storeut(cpu.c);","lni;"} },
	{ mnem="sta *p"     , opcode=0x52, {"adrlP","storeReg","alurA",         "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P=A", ccode={"storep(cpu.a);","lni;"} },
	{ mnem="stb *p"     , opcode=0x5A, {"adrlP","storeReg","alurB",         "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P=B", ccode={"storep(cpu.b);","lni;"} },
	{ mnem="stc *p"     , opcode=0x5B, {"adrlP","storeReg","alurC",         "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P=C", ccode={"storep(cpu.c);","lni;"} },
	{ mnem="sta *q"     , opcode=0x54, {"adrlQ","storeReg","alurA",         "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q=A", ccode={"storeq(cpu.a);","lni;"} },
	{ mnem="stb *q"     , opcode=0x5C, {"adrlQ","storeReg","alurB",         "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q=B", ccode={"storeq(cpu.b);","lni;"} },
	{ mnem="stc *q"     , opcode=0x5D, {"adrlQ","storeReg","alurC",         "memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q=C", ccode={"storeq(cpu.c);","lni;"} },
	{ mnem="lda *p"     , opcode=0x53, {"adrlP","loadReg","memSaveA",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*P, update zero flag", ccode={"cpu.a=loadp; setzf(cpu.a);","lni;"} },
	{ mnem="ldb *p"     , opcode=0x5E, {"adrlP","loadReg","memSaveB",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*P, update zero flag", ccode={"cpu.b=loadp; setzf(cpu.b);","lni;"} },
	{ mnem="ldc *p"     , opcode=0x5F, {"adrlP","loadReg","memSaveC",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*P, update zero flag", ccode={"cpu.c=loadp; setzf(cpu.c);","lni;"} },
	{ mnem="lda *q"     , opcode=0x55, {"adrlQ","loadReg","memSaveA",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*Q, update zero flag", ccode={"cpu.a=loadq; setzf(cpu.a);","lni;"} },
	{ mnem="ldb *q"     , opcode=0x61, {"adrlQ","loadReg","memSaveB",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*Q, update zero flag", ccode={"cpu.b=loadq; setzf(cpu.b);","lni;"} },
	{ mnem="ldc *q"     , opcode=0x62, {"adrlQ","loadReg","memSaveC",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*Q, update zero flag", ccode={"cpu.c=loadq; setzf(cpu.c);","lni;"} },
	{ mnem="sta *p++"   , opcode=0xC0, {"adrlP","storeReg","alurA",  "incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P++=A", ccode={"storepinc(cpu.a);","lni;"} },
	{ mnem="stb *p++"   , opcode=0xC1, {"adrlP","storeReg","alurB",  "incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P++=B", ccode={"storepinc(cpu.b);","lni;"} },
	{ mnem="stc *p++"   , opcode=0xC2, {"adrlP","storeReg","alurC",  "incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*P++=C", ccode={"storepinc(cpu.c);","lni;"} },
	{ mnem="sta *q++"   , opcode=0xC3, {"adrlQ","storeReg","alurA",  "incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q++=A", ccode={"storeqinc(cpu.a);","lni;"} },
	{ mnem="stb *q++"   , opcode=0xC4, {"adrlQ","storeReg","alurB",  "incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q++=B", ccode={"storeqinc(cpu.b);","lni;"} },
	{ mnem="stc *q++"   , opcode=0xC5, {"adrlQ","storeReg","alurC",  "incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="*Q++=C", ccode={"storeqinc(cpu.c);","lni;"} },
	{ mnem="lda *p++"   , opcode=0xC6, {"adrlP","loadReg","memSaveA","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*P++, update zero flag", ccode={"cpu.a=loadpinc; setzf(cpu.a);","lni;"} },
	{ mnem="ldb *p++"   , opcode=0xC7, {"adrlP","loadReg","memSaveB","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*P++, update zero flag", ccode={"cpu.b=loadpinc; setzf(cpu.b);","lni;"} },
	{ mnem="ldc *p++"   , opcode=0xC8, {"adrlP","loadReg","memSaveC","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*P++, update zero flag", ccode={"cpu.c=loadpinc; setzf(cpu.c);","lni;"} },
	{ mnem="lda *q++"   , opcode=0xC9, {"adrlQ","loadReg","memSaveA","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="A=*Q++, update zero flag", ccode={"cpu.a=loadqinc; setzf(cpu.a);","lni;"} },
	{ mnem="ldb *q++"   , opcode=0xCA, {"adrlQ","loadReg","memSaveB","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="B=*Q++, update zero flag", ccode={"cpu.b=loadqinc; setzf(cpu.b);","lni;"} },
	{ mnem="ldc *q++"   , opcode=0xCB, {"adrlQ","loadReg","memSaveC","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="C=*Q++, update zero flag", ccode={"cpu.c=loadqinc; setzf(cpu.c);","lni;"} },
	
	{ category = "16-bit Load/Store", catlet="W" },
	{ mnem="ldp imm16"  , opcode=0x21, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=imm16", ccode={"loadimm161","loadimm162","cpu.p=wordut; lni;"} },
	{ mnem="ldq imm16"  , opcode=0x23, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=imm16", ccode={"loadimm161","loadimm162","cpu.q=wordut; lni;"} },
	{ mnem="lds imm16"  , opcode=0x25, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adwrUT","adwSaveS","instrNext"}, desc="S=imm16", ccode={"loadimm161","loadimm162","cpu.s=wordut; lni;"} },
	{ mnem="ldv imm16"  , opcode=0x22, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adwrUT","adwSaveV","instrNext"}, desc="V=imm16", ccode={"loadimm161","loadimm162","cpu.v=wordut; lni;"} },
	{ mnem="ldp *s+imm8", opcode=0x7A, {"loadImmedT","instrSub1"}, {"loadStackRel161","instrSub2"}, {"loadStackRel162","instrSub3"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*S+imm8", ccode={"loadimmedt","loadstackrel161","loadstackrel162","cpu.p=wordut; lni;"} },
	{ mnem="ldq *s+imm8", opcode=0x7B, {"loadImmedT","instrSub1"}, {"loadStackRel161","instrSub2"}, {"loadStackRel162","instrSub3"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*S+imm8", ccode={"loadimmedt","loadstackrel161","loadstackrel162","cpu.p=wordut; lni;"} },
	{ mnem="stp *s+imm8", opcode=0x7E, {"loadImmedT","instrSub1"}, {"storeStackRel161","alurPH","instrSub2"}, {"storeStackRel162","alurPL","instrSub3"}, {"instrNext"}, desc="*S+imm8=P", ccode={"loadimmedt","storestackrel161(cpu.p);","storestackrel162(cpu.p);","lni;"} },
	{ mnem="stq *s+imm8", opcode=0x7F, {"loadImmedT","instrSub1"}, {"storeStackRel161","alurQH","instrSub2"}, {"storeStackRel162","alurQL","instrSub3"}, {"instrNext"}, desc="*S+imm8=Q", ccode={"loadimmedt","storestackrel161(cpu.q);","storestackrel162(cpu.q);","lni;"} },
	{ mnem="ldp *imm16" , opcode=0x68, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"loadUTU","adwIncUT","adwSaveP","instrSub3"}, {"adrlP","loadRegT","instrSub4"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*imm16", ccode={"loadimm161","loadimm162","cpu.p=wordut; cpu.u=loadut;","cpu.t=loadpp1;","cpu.p=wordut; lni;"} }, -- 0x69
	{ mnem="ldq *imm16" , opcode=0x6A, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"loadUTU","adwIncUT","adwSaveQ","instrSub3"}, {"adrlQ","loadRegT","instrSub4"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*imm16", ccode={"loadimm161","loadimm162","cpu.q=wordut; cpu.u=loadut;","cpu.t=loadqp1;","cpu.q=wordut; lni;"} }, -- 0x6B
	{ mnem="stp *imm16" , opcode=0x6C, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"storeUT","alurPH","instrSub3"}, {"storeUT","adrInc","alurPL","instrSub4"}, {"instrNext"}, desc="*imm16=P", ccode={"loadimm161","loadimm162","storeut(hibyte(cpu.p));","storeutp1(lobyte(cpu.p));","lni;"} }, -- 0x6D
	{ mnem="stq *imm16" , opcode=0x6E, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"storeUT","alurQH","instrSub3"}, {"storeUT","adrInc","alurQL","instrSub4"}, {"instrNext"}, desc="*imm16=Q", ccode={"loadimm161","loadimm162","storeut(hibyte(cpu.q));","storeutp1(lobyte(cpu.q));","lni;"} }, -- 0x6F
	{ mnem="ldp *p"     , opcode=0x92, {"adrlP","load161","instrSub1"}, {"adrlP","load162","instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*P", ccode={"cpu.u=loadp;","cpu.t=loadpp1;","cpu.p=wordut; lni;"} },
	{ mnem="ldq *p"     , opcode=0x93, {"adrlP","load161","instrSub1"}, {"adrlP","load162","instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*P", ccode={"cpu.u=loadp;","cpu.t=loadpp1;","cpu.q=wordut; lni;"} },
	{ mnem="ldp *q"     , opcode=0x94, {"adrlQ","load161","instrSub1"}, {"adrlQ","load162","instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*Q", ccode={"cpu.u=loadq;","cpu.t=loadqp1;","cpu.p=wordut; lni;"} },
	{ mnem="ldq *q"     , opcode=0x95, {"adrlQ","load161","instrSub1"}, {"adrlQ","load162","instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*Q", ccode={"cpu.u=loadq;","cpu.t=loadqp1;","cpu.q=wordut; lni;"} },
	{ mnem="stp *q"     , opcode=0x7C, {"adrlQ","store161","alurPH","instrSub1"}, {"adrlQ","store162","alurPL","instrSub2"}, {"instrNext"}, desc="*Q=P", ccode={"storeq(hibyte(cpu.p));","storeqp1(lobyte(cpu.p));","lni;"} },
	{ mnem="stq *p"     , opcode=0x7D, {"adrlP","store161","alurQH","instrSub1"}, {"adrlP","store162","alurQL","instrSub2"}, {"instrNext"}, desc="*P=Q", ccode={"storep(hibyte(cpu.q));","storepp1(lobyte(cpu.q));","lni;"} },
	{ mnem="ldq *p++"   , opcode=0xCC, {"adrlP","load161","instrSub1"}, {"adrlP","load162","instrSub2","incP2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Q=*P++++", ccode={"cpu.u=loadpinc;","cpu.t=loadpinc;","cpu.q=wordut; lni;"} },
	{ mnem="ldp *q++"   , opcode=0xCD, {"adrlQ","load161","instrSub1"}, {"adrlQ","load162","instrSub2","incQ2"}, {"adwrUT","adwSaveP","instrNext"}, desc="P=*Q++++", ccode={"cpu.u=loadqinc;","cpu.t=loadqinc;","cpu.p=wordut; lni;"} },
	{ mnem="stp *q++"   , opcode=0xCE, {"adrlQ","store161","alurPH","instrSub1"}, {"adrlQ","store162","alurPL","instrSub2","incQ2"}, {"instrNext"}, desc="*Q++++=P", ccode={"storeqinc(hibyte(cpu.p));","storeqinc(lobyte(cpu.p));","lni;"} },
	{ mnem="stq *p++"   , opcode=0xCF, {"adrlP","store161","alurQH","instrSub1"}, {"adrlP","store162","alurQL","instrSub2","incP2"}, {"instrNext"}, desc="*P++++=Q", ccode={"storepinc(hibyte(cpu.q));","storepinc(lobyte(cpu.q));","lni;"} },
	
	{ category = "Moves", catlet="M" },
	{ mnem="lda b"      , opcode=0x80, {"alurB" ,"aluOpMov","aluSaveA","instrNext"}, desc="A=B", ccode={"cpu.a=cpu.b; lni;"} },
	{ mnem="lda c"      , opcode=0x81, {"alurC" ,"aluOpMov","aluSaveA","instrNext"}, desc="A=C", ccode={"cpu.a=cpu.c; lni;"} },
	{ mnem="ldb a"      , opcode=0x82, {"alurA" ,"aluOpMov","aluSaveB","instrNext"}, desc="B=A", ccode={"cpu.b=cpu.a; lni;"} },
	{ mnem="ldb c"      , opcode=0x83, {"alurC" ,"aluOpMov","aluSaveB","instrNext"}, desc="B=C", ccode={"cpu.b=cpu.c; lni;"} },
	{ mnem="ldc a"      , opcode=0x84, {"alurA" ,"aluOpMov","aluSaveC","instrNext"}, desc="C=A", ccode={"cpu.c=cpu.a; lni;"} },
	{ mnem="ldc b"      , opcode=0x85, {"alurB" ,"aluOpMov","aluSaveC","instrNext"}, desc="C=B", ccode={"cpu.c=cpu.b; lni;"} },
	{ mnem="lda pl"     , opcode=0x86, {"alurPL","aluOpMov","aluSaveA","instrNext"}, desc="A=P&FF", ccode={"cpu.a=lobyte(cpu.p); lni;"} },
	{ mnem="lda ph"     , opcode=0x87, {"alurPH","aluOpMov","aluSaveA","instrNext"}, desc="A=P>>8", ccode={"cpu.a=hibyte(cpu.p); lni;"} },
	{ mnem="lda ql"     , opcode=0x88, {"alurQL","aluOpMov","aluSaveA","instrNext"}, desc="A=Q&FF", ccode={"cpu.a=lobyte(cpu.q); lni;"} },
	{ mnem="lda qh"     , opcode=0x89, {"alurQH","aluOpMov","aluSaveA","instrNext"}, desc="A=Q>>8", ccode={"cpu.a=hibyte(cpu.q); lni;"} },
	{ mnem="ldb pl"     , opcode=0x37, {"alurPL","aluOpMov","aluSaveB","instrNext"}, desc="B=P&FF", ccode={"cpu.b=lobyte(cpu.p); lni;"} },
	{ mnem="ldc ph"     , opcode=0x38, {"alurPH","aluOpMov","aluSaveC","instrNext"}, desc="C=P>>8", ccode={"cpu.c=hibyte(cpu.p); lni;"} },
	{ mnem="ldb ql"     , opcode=0x39, {"alurQL","aluOpMov","aluSaveB","instrNext"}, desc="B=Q&FF", ccode={"cpu.b=lobyte(cpu.q); lni;"} },
	{ mnem="ldc qh"     , opcode=0x3A, {"alurQH","aluOpMov","aluSaveC","instrNext"}, desc="C=Q>>8", ccode={"cpu.c=hibyte(cpu.q); lni;"} },
	{ mnem="ldp q"      , opcode=0x8A, {"adwlQ" ,           "adwSaveP","instrNext"}, desc="P=Q", ccode={"cpu.p=cpu.q; lni;"} },
	{ mnem="ldp s"      , opcode=0x8B, {"adwlS" ,           "adwSaveP","instrNext"}, desc="P=S", ccode={"cpu.p=cpu.s; lni;"} },
	{ mnem="ldp v"      , opcode=0x8C, {"adwlV" ,           "adwSaveP","instrNext"}, desc="P=V", ccode={"cpu.p=cpu.v; lni;"} },
	{ mnem="ldp i"      , opcode=0x8D, {"adwlI" ,           "adwSaveP","instrNext"}, desc="P=I", ccode={"cpu.p=cpu.i; lni;"} },
	{ mnem="ldp cb"     , opcode=0x91, {"adwrCB",           "adwSaveP","instrNext"}, desc="P=(C<<8)+B", ccode={"cpu.p=wordcb; lni;"} },
	{ mnem="ldq cb"     , opcode=0xE0, {"adwrCB",           "adwSaveQ","instrNext"}, desc="Q=(C<<8)+B", ccode={"cpu.q=wordcb; lni;"} },
	{ mnem="ldq p"      , opcode=0x8E, {"adwlP" ,           "adwSaveQ","instrNext"}, desc="Q=P", ccode={"cpu.q=cpu.p; lni;"} },
	{ mnem="lds p"      , opcode=0x8F, {"adwlP" ,           "adwSaveS","instrNext"}, desc="S=P", ccode={"cpu.s=cpu.p; lni;"} },
	{ mnem="ldv p"      , opcode=0x90, {"adwlP" ,           "adwSaveV","instrNext"}, desc="V=P", ccode={"cpu.v=cpu.p; lni;"} },
},

aliases = {
	["jpz imm8"] = {"jeq imm8"},
	["jnz imm8"] = {"jne imm8"},
	["jmp q"   ] = {"ret"     },
},

}
